• Functional implementations

  • SystemC
  • C++
  • VHDL

• Graphical specifications
  
  • UML Sequence Diagrams (XMI)
  • UML State Machines (XMI)
  • UML Timing Diagrams (XMI)
  • UML Composite Structure Diagram
  • SysML Assemblies
  • Manual CDG Modeling

and combinations of these.

The tool allows formal performance analysis concerning the intermediate formal system model, the communication dependency graph (CDG) and an architectural meta model. A screenshot showing the tool analyzing a SystemC model of a viterbi decoder is shown above. The formal performance analysis is able to analyze the system model even at the design stage using UML/SysML models. Some already implemented and upcoming analysis methods of the formal performance analysis are:

• Determination of minimum/maximum input/out data rates

• Calculation of path/system latencies

• Conflict analysis, resource allocation and binding towards a specified architecture (e.g. with SysML assemblies)

• Recognition of inter-process synchronization

• Determination of data loss

• Recognition of deadlocks defined by the communication structure

• Inclusion of common temporal environment models

• Buffer sizing

• Resource utilization

The results of the formal analysis can be exported as

• SystemC simulation models (including traces)
  

• UML2 Sequence Diagrams (XMI)
  

• UML2 Timing Diagrams (XMI)