Publications
2012
Stefan Stattelmann, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel
Towards Accurate Source-Level Annotation of Low-Level Properties Obtained from Optimized Binary Code
contribution to a book, System Specification and Design Languages - Kazmierski, Tom J.; Morawiec, Adam (Eds.); Lecture Notes in Electrical Engineering, Vol. 106; Springer Verlag
2011
Andreas Braun, Oliver Bringmann, Wolfgang Rosenstiel
Virtuelle Prototypen unter Einsatz der TTWorkbench
article, Embedded Design
Sebastian Reiter, Andreas Braun, Rico Hauke, Alexander Leonhardi, Oliver Bringmann, Wolfgang Rosenstiel
Automatisierte Leistungsevaluierung des MOST-High-Protokolls mittels Virtueller Prototypen
article, Elektronik Informationen 9 2011
Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel
Dominator Homomorphism Based Code Matching for Source-Level Simulation of Embedded Software
proceeding, CODES+ISSS'11, 2011, Taipei, Taiwan.
Zhongjian Liang
Konzeption und Implementierung eines virtuellen MOST Bus Modells zur Verifikation von Zuverlässigkeitsmechanismen
diploma thesis,
Andreas Braun, Oliver Bringmann, Wolfgang Rosenstiel
Test Description and Automation for Software Verification on Virtual Prototypes using the TTWorkbench
proceeding,
Wolfgang Rosenstiel, Oliver Bringmann
Report 2009 - 2010: Microelectronic System Design - FZI, Department of Computer Engineering - University of Tuebingen
other, http://www.fzi.de/
Sebastian Reiter, Andreas Braun, Rico Hauke, Alexander Leonhardi, Oliver Bringmann, Wolfgang Rosenstiel
Automated Performance Evaluation of the MOST High Protocol Using Virtual Prototypes
proceeding, International MOST Conference & Exhibition 2011
Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel
Fast and Accurate Source-Level Simulation of Software Timing Considering Complex Code Optimizations
proceeding, 48th Design Automation Conference (DAC), San Diego, 2011
Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel
Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems
proceeding, Design, Automation & Test in Europe (DATE 2011), Grenoble, France
2010
Matthias Thoma
Modellierung und optimierte Abbildung eingebetteter Software auf Multi-/Many-Core Systeme
diploma thesis,
Xu Yijun
Konzipierung und Implementierung eines SystemC Modells im komponentenbasierten Entwurfsfluss unter Berücksichtigung Software-Scheduling
assignment,
Abdellatif Laaroussi
Erweiterung und Optimierung eines Frameworks zur Erfassung und Transformation von SystemC-Modellen
assignment,
Yang Fan
Plattformunabhängige Funktionalitätsabstraktion eingebetteter Software-Systeme zur automatisierten Abbildungskonfiguration
diploma thesis,
Martin Oexner
Automatische Generierung virtueller Prototypen zur zeitbehafteten Simulation von RT-Java-Komponenten
diploma thesis,
Ze Li
Weiterentwicklung einer SystemC-Umgebung für Eclipse
assignment,
Andreas Braun, Stefan Lämmermann, Oliver Bringmann, Wolfgang Rosenstiel
Virtual Prototyping in der Hardware- und Software-Entwicklung vernetzter Steuergeräte
proceeding, AutoTest, Stuttgart, 2010.
Mahmoud Amraune
TTCN-3 basierte Testmodellierung für Virtuelle Prototypen am Beispiel MOST
assignment,
Adil Bouqfoul (Betreuer: Andreas Braun, Sebastian Reiter)
Vergleich zwischen virtueller und realer MOST Performanz Analyse
assignment,
Martin Radetzki, Oliver Bringmann, Wolfgang Nebel, Markus Olbrich, Felix Salfelder, Ulf Schlichtmann
Robustheit nanoelektronischer Schaltungen und Systeme
proceeding, Zuverlässigkeit und Entwurf, 4. GMM/GI/ITG-Fachtagung, Wildbad Kreuth
B. Sander, J. Schnerr, O. Bringmann, W. Rosenstiel
Entwurfsraumexploration eingebetteter Multi-Core-Systeme auf Architekturebene unter Berücksichtigung von Performanz, Energie und Zuverlässigkeit
proceeding, edaWorkshop, Hannover, 2010
Stefan Stattelmann, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel
Reconstructing Line References from Optimized Binary Code for Source-Level Annotation
proceeding, Forum on specification & Design Languages (FDL), Southampton, UK
Stefan Stattelmann, Florian Martin
On the Use of Context Information for Precise Measurement-Based Execution Time Estimation
proceeding, 10th International Workshop on Worst-Case Execution-Time Analysis, Brussels, Belgium
M. Müller, A. Braun, J. Gerlach, W. Rosenstiel, D. Nienhüser, J. M. Zöllner, O. Bringmann
Design of an Automotive Traffic Sign Recognition System Targeting a Multi-Core SoC Implementation
proceeding, Design, Automation and Test in Europe (DATE), Dresden, 2010
Stefan Lämmermann, Alexander Jesser, Alexander Viehl, Jürgen Ruf, Lars Hedrich, Thomas Kropf, Wolfgang Rosenstiel
Towards Assertion-Based Verification of Heterogeneous System Designs
proceeding, DATE'10: Proceedings of Designs, Automation, and Test in Europe conference and exhibition, Dresden, 2010
Andreas Braun, Markus Becht, Oliver Bringmann, Wolfgang Rosenstiel
Automated Determination of Worst-Case Scenarios for the MOST Optical Physical Layer Specification Point 3
proceeding, International MOST Conference & Exhibition, Frankfurt, 2010
Andreas Braun, Oliver Bringmann, Wolfgang Rosenstiel
MHP Protocol Verification and Performance Analysis of Different MHP Configurations Using Virtual Prototypes
proceeding, International MOST Conference & Exhibition, Frankfurt, 2010
Andreas Braun, Djones Lettnin, Oliver Bringmann, Wolfgang Rosenstiel
Simulation-Based Verification of the MOST NetInterface Specification Revision 3.0
proceeding, Design, Automation and Test in Europe (DATE), Dresden, 2010
Jochen Zimmermann, Michael Pressler, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel
Model-based virtual prototyping for early automotive software systems evaluation
proceeding, M-BED 2010, MARTE User Group Workshop at DATE'10
Jürgen Schnerr, Oliver Bringmann, Matthias Krause, Alexander Viehl, Wolfgang Rosenstiel
SystemC-Based Performance Analysis of Embedded Systems
contribution to a book, Gabriela Nicolescu, Pieter J. Mosterman - Model-Based Design for Embedded Systems, CRC Press, 2010
2009
Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
proceeding, IEEE International Conference on Self-Adaptive and Self-Organizing Systems, p.126-135, San Francisco, 2009
Wolfgang Rosenstiel, Oliver Bringmann
Report 2006 - 2008: Microelectronic System Design - FZI, Department of Computer Engineering - University of Tuebingen
other, http://www.fzi.de/
Hang Su
Entwicklung eines Generators zur Ermittlung von On-Chip-Temperaturen mit SystemC-AMS
assignment,
Amine Benchaalal
Extraktion temporaler Analysemodelle aus SystemC-Beschreibungen eingebetteter Softwaresysteme
diploma thesis,
Andreas Mauderer
Entwicklung eines hybriden Verfahrens zur Topologie-Exploration von verteilten eingebetteten Systemen in der Anwendungsdomäne Automobil
diploma thesis,
Minda Wang
Entwicklung eines Entwurfswerkzeugs zur Modelltransformation von MATLAB/Simulink nach SystemC am Beispiel einer Verkehrszeichenerkennung
diploma thesis,
A. Viehl, J. Dukadinov, O. Bringmann, W. Rosenstiel
TRANSYSCTOR: A General Methodology and Framework for Rule-Based Transformation and Refactoring of
SystemC Designs
proceeding, Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Okinawa, Japan
A. Viehl, M. Pressler, O. Bringmann, W. Rosenstiel
White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling
proceeding, DATE '09: Proceedings of the IEEE/ACM conference on Design, automation and test in Europe
A. Viehl, B. Sander, O. Bringmann, W. Rosenstiel
Analysis of Non-Functional Properties of MPSoC Designs
contribution to a book, Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification; Editor: Martin Radetzki; Springer Verlag
Matthias Krause, Oliver Bringmann and Wolfgang Rosenstiel
Verification of AUTOSAR Software by SystemC-Based Virtual Prototyping
contribution to a book, Hardware-dependent Software - Principles and Practice.
Editors: Wolfgang Ecker, Wolfgang Müller, Rainer Dömer.
Springer, 2009.
Björn Sander, Jürgen Schnerr, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel
Schnelle, zyklengenaue Abschätzung der Leistungsaufnahme eingebetteter Prozessoren auf Systemebene
proceeding, edaWorkshop, Dresden
Björn Sander, Jürgen Schnerr, Oliver Bringmann
ESL Power Analysis of Embedded Processors for Temperature and Reliability Estimations
proceeding, International Conference on Hardware/Software Codesign and System Synthesis, Grenoble, France
Alexander Viehl, Michael Pressler, Oliver Bringmann
Bottom-Up Performance Analysis Considering Time Slice Based Software Scheduling at System Level
proceeding, International Conference on Hardware/Software Codesign and System Synthesis, Grenoble, France
Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel
Network-on-Chip Architecture Exploration Framework
proceeding, Euromicro Conference on Digital System Design (DSD), Patras, Greece
Jochen Zimmermann, Axel Braun, Oliver Bringmann, Wolfgang Rosenstiel
Integration of High-Level Synthesis in ESL Platform Modeling by Automated Generation of Protocol Adapters
proceeding, Proceedings of the 7th International Conference on Communications, Circuits and Systems (ICCCAS), San Jose, California, USA, July 23-25, 2009
Andreas Braun, Oliver Bringmann, Wolfgang Rosenstiel
Validierung der MOST-Spezifikation Revision 3.0
article, Hanser automotive, März/April 2009
2008
Mohamed Bawadekji
Redesign eines DLX-Prozessors
assignment,
Dominik Englert
Entwurf und Implementierung eines Konzepts zur Anbindung eines Echtzeitbetriebssystemmodells an einen Instruction-Set-Simulator
diploma thesis,
Amine Benchaalal
Synthese temporaler Analysemodelle aus UML2 Datenflussbeschreibungen
assignment,
Lu Wang
Evaluierung von Systems-on-Chip für den anwendungsrobusten Entwurf
assignment,
Fan Yang
Simulationsmodellgenerierung von verteilten eingebetteten Systemen
assignment,
Jun Xu
Controllersynthese zur konfliktfreien Zuteilung von Kommunikationsressourcen
assignment,
Michael Pressler
Analytische Performanzbewertung verteilter eingebetteter Systeme unter Berücksichtigung von Software-Scheduling-Strategien
diploma thesis,
Jordan Dukadinov
Entwicklung eines Frameworks zur regelbasierten Codetransformation von SystemC-Modellen
assignment,
Murat Bayindir
Aufbau einer generischen XML-Spezifikationsdatenbasis mit Anbindung von Import- und Exportfiltern
diploma thesis,
Wolfgang Wittner
Modellierung und Generierung von On-Chip-Netzwerken mit UML unter Berücksichtigung von IP-XACT Komponentenbeschreibungen
diploma thesis,
J. Zimmermann, O. Bringmann, J. Gerlach, F. Schäfer, U. Nageldinger
Comprehensive platform and component modeling of heterogeneous interconnected systems
proceeding, Forum on specification & Design Languages (FDL), Stuttgart, 2008
M. Krause, D. Englert, O. Bringmann and W. Rosenstiel
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation
proceeding, 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), Atlanta, GA, USA, 2008.
A. Viehl, B. Sander, O. Bringmann, W. Rosenstiel
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties
proceeding, Forum on specification & Design Languages (FDL), Stuttgart, 2008
A. Viehl, B. Sander, O. Bringmann, F. Yang, W. Rosenstiel
Quantitative Bewertung nicht-funktionaler Systemanforderungen von System-on-Chip-Entwürfen
proceeding, DASS, Dresden, 2008
J. Schnerr, O. Bringmann, A. Viehl, W. Rosenstiel
High-Performance Timing Simulation of Embedded Software
proceeding, 45th Design Automation Conference (DAC), Anaheim, 2008
J. Zimmermann, O. Bringmann, J. Gerlach, F. Schäfer, U. Nageldinger
Model-Based Platform Composition and Generation of Virtual Prototypes for Interconnected Microelectronic Systems
proceeding, edaWorkshop, Hannover, 2008
J. Zimmermann, O. Bringmann, J. Gerlach, F. Schäfer, U. Nageldinger
Holistic System Modeling and Refinement of Interconnected Microelectronic Systems
proceeding, MARTE Workshop, München, 2008
Andreas Braun, Oliver Bringmann, Wolfgang Rosenstiel
Validation of the MOST150 Specification by Virtual Prototyping
article, MOST Informative, Issue 3, September, 2008
A. Bernauer, D. Fritz, B. Sander, O. Bringmann, W. Rosenstiel
Current state of AsoC design methodology
proceeding, Dagstuhl Seminar, 2008
2007
Xiaoming Zhang
Modellierung und Simulation vernetzter Steuergeräte im Automobil durch einen virtuellen Prototypen in SystemC
diploma thesis,
Dominik Englert
Entwurf und Implementierung abstrakter Bus-Kommunikationsverfahren in SystemC
assignment,
T. Schönwald, O.Bringmann, W. Rosenstiel
Region-Based Routing Algorithm for Network-on-Chip Architectures
proceeding, 25th IEEE NORCHIP Conference, Aalborg Dänemark, 2007
A. Viehl, O. Bringmann, W. Rosenstiel
Performance-Aware Communication Architecture Synthesis
proceeding, Synthesis And System Integration of Mixed Information Technologies (SASIMI), Sapporo, 2007
A. Viehl, M. Schwarz, O. Bringmann, W. Rosenstiel
Probabilistic Performance Risk Analysis at System-Level
proceeding, 5th International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Salzburg, 2007
W. Stechele, O. Bringmann, J. Zeppenfeld, A. Herkersdorf, R. Ernst, K. Hojenski, P. Janacik, F. Rammig, J. Teich, D. Ziener, N. Wehn
Concepts for Autonomic Integrated Systems (AIS)
proceeding, edaWorkshop, Hannover, 2007
T. Schönwald, J. Zimmermann, O.Bringmann, W. Rosenstiel
Fully Adaptive Fault Tolerant Routing Algorithm for Network-on-Chip Architectures
proceeding, 10th Euromicro Conference on Digital System Design, Lübeck, 2007
B. Sander, O. Bringmann, W. Rosenstiel
Applikationsspezifische Zuverlässigkeitsbewertung von MPSoCs
proceeding, edaWorkshop, Hannover, 2007
A. Viehl, M. Schwarz, O. Bringmann, W. Rosenstiel
Ein hybrider Ansatz zur Abschätzung von Performanz und Leistungsverbrauch auf Systemebene
proceeding, edaWorkshop, Hannover, 2007
T. Schönwald, J. Zimmermann, O. Bringmann, W. Rosenstiel
Ein Framework zur automatisierten Generierung von Network-on-Chips in SystemC
proceeding, edaWorkshop, Hannover, 2007
A. Viehl, M. Schwarz, O. Bringmann, W. Rosenstiel
A Hybrid Approach for System-Level Design Evaluation
contribution to a book, Embedded System Design: Topics, Techniques and Trends; Springer Verlag; International Federation for Information Processing (IFIP)
M. Krause, O. Bringmann, A. Hergenhan, G. Tabanoglu, W. Rosenstiel
Timing Simulation of Interconnected AUTOSAR Software-Components
proceeding, Design, Automation and Test in Europe (DATE), Nizza, 2007
W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D .Ziener
Autonomic MPSoCs for Reliable Systems
proceeding, Zuverlässigkeit und Entwurf, GMM-Fachbericht, VDE Verlag, Berlin
B. Sander, O. Bringmann, T. Schönwald, J. Schnerr, W. Rosenstiel
Applikationsspezifische Zuverlässigkeitsbewertung von Multiprocessor Systems-on-Chip auf Systemebene
other, Zuverlässigkeit und Entwurf, GMM-Fachbericht, VDE Verlag, Berlin
M. Krause, O. Bringmann, W. Rosenstiel
Target Software Generation: An Approach for Automatic Mapping of SystemC Specifications onto Real-Time Operating Systems
article, Design Automation for Embedded Systems, Volume 10, Issue 4, Springer.
A. Siebenborn, A. Viehl, O. Bringmann,W.Rosenstiel
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
proceeding, Proceedings of the 12th Asia and South Pacific Design Automation Conference ASP-DAC, Yokohama, 2007
2006
Gökhan Tabanoglu
Modellierung und Implementierung eines funktionalen FlexRay-Busmodells in SystemC
diploma thesis,
Dereje Kebede
Untersuchung zur Modellierung und Bewertung eingebetteter Systeme mit UML2 State-Machines
assignment,
Markus Schwarz
Architekturspezifisches Laufzeitprofiling von SystemC-Modellen zur Abschätzung der Performanz und des Leistungsverbrauchs auf Systemebene
diploma thesis,
A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel
Organic Computing at the System on Chip Level
proceeding, In Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006). Springer
Andreas Bernauer, O. Bringmann, , Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
An Architecture for Runtime Evaluation of SoC Reliability
proceeding, In INFORMATIK 2006 - Informatik für Menschen, volume P-93 of GI-Edition - Lecture Notes in Informatics, pages 177-185, Köllen Verlag
Wolfgang Klingauf, Robert Günzel, O. Bringmann, Pavel Parfuntseu, Mark Burton
GreenBus - A Generic Interconnect Fabric for Transaction Level Mod
proceeding, 43rd Design Automation Conference (DAC), San Francisco, CA, USA, July 2006
Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Walter Stechele, O. Bringmann, W. Rosenstiel
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs
proceeding, IFIP Conference on Biologically Inspired Cooperative Computing, Santiago de Chile, 2006
A. Viehl, O. Bringmann, , T. Schönwald
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design
proceeding, Design, Automation and Test in Europe (DATE), Munich, 2006
M. Krause, O. Bringmann, W. Rosenstiel
A SystemC-based Software and Communication Refinement Framework for Distributed Embedded Systems
proceeding, 13th Workshop on Synthesis And System Integration of Mixed Information Technologies, Nagoya, 2006
M. Krause, O. Bringmann, W. Rosenstiel
Communication Refinement and Target Software Generation using SystemC
proceeding, GI/ITG/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, 2006
A. Viehl, O. Bringmann, W. Rosenstiel
Virtual Prototyping und frühe Evaluierung von Systems-on-Chip mit UML2 und SysML
proceeding, GI/ITG/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, 2006
2005
Dmitri Benderman
Entwurf und Implementierung eines Ansatzes zur automatischen Abbildung von SystemC-Spezifikationen auf ein Echtzeitbetriebssystem
diploma thesis,
Timo Schönwald
Spezifikationsbasierte Generierung von strukturellen SystemC-Modellen aus UML und SysML
diploma thesis,
Simon Kramer
Entwicklung einer SystemC-Umgebung für Eclipse
assignment,
Clemens Gebhard
Konflikterkennung und Ressourcenallokation in eingebetteten Systemen
assignment,
Christian Renner
Verhaltensvisualisierung eingebetteter Systeme durch UML2-Sequenzdiagramme
assignment,
A. Braun, J. Gerlach, W. Rosenstiel, A. Siebenborn, O. Bringmann
SystemC-Based Communication and Performance Analysis
proceeding, Forum on specification and Design Languages (FDL)
Lausanne, Switzerland, September 27-30, 2005.
O. Bringmann, A. Siebenborn, W. Rosenstiel
Conflict Analysis in Multiprocess Synthesis for Optimized System Integration
proceeding, IEEE/ACM/IFIP International Conference on Hardware - Software Codesign and System Synthesis (CODES-ISSS), New York, USA, Sept. 19-21, 2005
G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele
Towards a Framework and a Design Methodology for Autonomic SoC
proceeding, The 2nd IEEE International Conference on Autonomic Computing (ICAC-05), 13-16 June, Seattle, USA, Conference Proceedings
A. Viehl,, W. Rosenstiel
Performance Analysis of Sequence Diagrams for SoC Design
proceeding, 2nd UML for SoC Design Workshop at 42nd Design Automation Conference (DAC), Anaheim, California, 2005
J. Schnerr, O. Bringmann, W. Rosenstiel
Cycle Accurate Binary Tanslation for Simulation Acceleration in Rapid Prototyping of SoCs
proceeding, March 2005, Munich, Germany, Proceedings of the Design, Automation and Test in Europe (DATE) 2005, Pages: 792-797
G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, Walter Stechele
Towards a Framework and a Design Methodology for Autonomic SoC
proceeding, Proceedings Dynamically Reconfigurable Systems Self-Organization and Emergence, Architecture of Computing Systems (ARCS) 2005, Pages: 101-108.
2004
A. Siebenborn , O. Bringmann , W. Rosenstiel
Communication Analysis for System on Chip Design
contribution to a book, DATE, February 2004, Paris, France, Proceedings of the Design Automation and Test in Europe Conference (DATE) 2004, Pages: 648-653
A. Vörg, W. Rosenstiel
Automation of IP qualification and IP exchange
proceeding, Integration, the VLSI Journal, Elsevier, Vol 37/4 pp 323-352, 2004
O. Bringmann , A. Braun, W. Rosenstiel
Specification and Design Data Exchange of Micro Electronic Hardware/Software Systems using SystemC
proceeding, 6th NASA-ESA Workshop on Product Data Exchange - Open Standards for Model-Based Development, Friedrichshafen, 2004
A. Siebenborn , O. Bringmann , W. Rosenstiel
Communication Analysis for Network-on-Chip
proceeding, International Conference on Parallel Computing in Electrical Engineering (PARELEC), Dresden, 2004
A. Vörg, M. Radetzki, W. Rosenstiel
Measurement of IP Qualification Costs and Benefits
proceeding, DATE, February 2004, Paris, France, Proceedings of the Design Automation and Test in Europe Conference (DATE) 2004.
2003
J. Schnerr , G. Haug , W. Rosenstiel
Instruction Set Emulation for Rapid Prototyping of SoCs
proceeding, Design, Automation and Test in Europe (DATE) Conference and Exhibition, 2003, March 3-7, 2003, Pages: 562-567
O. Bringmann
Synchronisationsanalyse zur Multi-Prozess-Synthese
book, Logos-Verlag Berlin, 2003
2002
Antonio J. Ginés, Eduardo Peralías, Adoración Rueda, R. Seepold , N. Martinez
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects
contribution to a book, Design, Automation and Test in Europe (DATE) Conference and Exhibition, 2002, March 4-8, 2002, Pages: 310-315
R. Seepold , N. Martinez , A. Vörg , W. Rosenstiel, M. Radetzki, P. Neumann, J. Haase
A Qualification Platform for Design Reuse
proceeding, International Society for Quality Electronic Design (ISQED) 2002, San Jose, CA, USA, March 2002
A. Siebenborn, O. Bringmann, W. Rosenstiel
Worst-case performance analysis of parallel, communicating software processes
proceeding, CODES, May 2002, USA, Proceedings of the Tenth International Symposium on Hardware/Softwarw Codesign 2002, Vol., 2002 Pages: 37- 42
N. Martinez , A. Acosta Fernandez , F. Ruiz Moreno , R. Seepold
Multi-level analog/mixed-signal IP specification
proceeding, FDL, September 2002, France, Proceedings of FDL 2002, Vol. 1
Amtel, Forschungszentrum Informatik (FZI)-SIM
Tutorial on Intellectual Property (IP)",
lecture, Infineon Technologies and sci-worx
DAC, 2002, USA
C. Menn , O. Bringmann , W. Rosenstiel
Controller Estimation for FPGA Target Architectures During High-Level Synthesis
proceeding, Proceedings of ISSS, 2002
2001
C. Hansen , O. Bringmann,
A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis
contribution to a book, in "Virtual Components Design and Reuse" edited by R. Seepold and N. Martinez, Kluwer Academic Publishers, 2001.
R. Seepold , N. Martinez , editors
Virtual Components Design and Reuse
book, Kluwer Academic Publishers, ISBN0-7923-7261-1, 2001
R. Seepold
Standardization of System-Level IP
lecture, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und System - GI/ITG/GMM-Workshop, February 2001
A. Vörg , R. Seepold , N. Martinez , W. Rosenstiel
IP-Qualifizierung wiederverwendbarer Schaltungsbeschreibungen
proceeding, Präsentationen der 10. ITG-Fachtagung des 10. E.I.S.-Workshop 2001, Dresden, April 2001
R. Seepold
Specification and Standardization of System-Level IP
proceeding, IP Forum, May 14-15, 2001
P. J. Ashenden, J. P. Mermet, R. Seepold , editors
System-on-Chip Methodologies & Design Languages
book, Kluwer Academic Publishers, ISBN 0-7923-7393-6, June 2001
R. Seepold
Reuse of Virtual Components
proceeding, Diseño De Sistemas Embebidos HW/SW - Universidad de Cantabria (Summer School), Santander, Spain, July 2001
N. Martinez , E. Peralias, A. Acosta, A. Rueda
Analog/Mixed-Signal IP Modeling for Design Reuse
proceeding, DATE Conference, Munich, March 2001
A. Vörg , R. Seepold , N. Martinez , W. Rosenstiel
IP-Qualification, Reuse, IP-Packaging
proceeding, Forum on Design Languages 2001, Lyon, France, September 2001
M. Radetzki, P. Neumann, J. Haase, R. Seepold ,, N. Martinez , A. Vörg
Automated Qualification Flow for Soft IP
proceeding, Proceedings of the MEDEA+ Conference on Application-Oriented SoC Design, October 10-12, 2001, Veldhoven, The Netherlands
2000
G. Haug , U. Kebschull , W. Rosenstiel
Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren
proceeding, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen Workshop, Frankfurt a.M., Februar, 2000
G. Haug , U. Kebschull, W. Rosenstiel
A Hardware Platform for VLIW Based Emulation of Digital Designs
proceeding, Proceedings of Design, Automation and Test in Europe (D.A.T.E.), Paris, March 2000
A. Reutter, C. Buchholz , T. Bohn, K. Unger, J. Schneider
Ein umfassendes Wiederverwendungssystem fuer den industriellen Einsatz: Wiederverwendungsdatenbasis, Testbench-Generierung und Codeanalyse
lecture, 3. Workshop zum Förderschwerpunkt "Smart Systems Engineering" (SSE), Berlin, Germany, April 2000
C. Buchholz , W. Rosenstiel
Constraint-Based Specification of Complex Components
proceeding, International HDL Conference 2000 (HDLCON), San Jose, CA, USA, March 8-10, 2000
C. Buchholz , W. Rosenstiel
A Constraint-Based Design Methodology for Automated Composition with IPs
proceeding, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen Workshop, Frankfurt a.M., Februar, 2000
O. Bringmann
Hierarchische Synthese für anwendungsspezifische Prototypenimplementierungen
article, it + ti - Informationstechnik und Technische Informatik, Oldenbourg Verlag, 42. Jahrgang, Heft 2, 2000
O. Bringmann , W. Rosenstiel
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
proceeding, Proceedings of Design, Automation and Test in Europe (D.A.T.E.), Paris, March 2000
C. Hansen , M. Pröfrock, W. Rosenstiel
Transformation of Algorithmic Simulation Vector Sets for Automatic Reuse at RT Level
proceeding, Forum on Design Languages (FDL'00), Tübingen, Deutschland, September 2000
S. Schmitt , W. Rosenstiel
Untersuchungen zur Implementierung von Java-Laufzeitumgebungen für eingebettete Systeme
proceeding, NODE 2000, Erfurt, Oktober 2000
C. Hansen , W. Rosenstiel
Transformation of Algorithmic Simulation Vector Sets Considering Mapping Problems of I/O Operations
proceeding, High Level Design Validation and Test Workshop'00, Berkeley (CA), USA, November 2000
A. Hergenhan, W. Rosenstiel
Static Timing Analysis of Embedded Software on Modern Processor Architectures
proceeding, In: Proceedings of the Date 2000 Conference, Paris, France, 2000
A. Hergenhan , A. Siebenborn , W. Rosenstiel
Studies on Different Modeling Aspects for Tight Calculations of Worst Case Execution Time
contribution to a book, In: WIP-Proceedings of the 21th IEEE Real-Time Systems Symposium, Orlando, Florida, USA, 2000
1999
K. Weiß , T. Steckstor, W. Rosenstiel
Emulation of a Fast Reactive Embedded System using a Real Time Operating System
proceeding, DATE99, München, März 1999
K. Weiß, T. Steckstor, C. Nitsch, U. Kebschull, W. Rosenstiel
Performance Analysis of Real-Time Operating Systems by Emulation of an Embedded System
proceeding, RSP'99, Clearwater, Florida, USA, June 1999
K. Weiß , T. Steckstor, G. Koch , W. Rosenstiel
Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System
proceeding, IEEE Symposiom of Field Programmable Gate Array 1999, Monterey, CA
S. Schmitt , W. Rosenstiel
Konzeption und Realisierung eingebetteter Systeme im Internet
proceeding, Bericht des Wilhelm-Schickard-Instituts für Informatik, Januar 1999
A. Reutter, C. Buchholz , J. Schneider, T. Bohn
A Prototype of a Comprehensive Reuse System for Industrial Usage
proceeding, IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France, December 14-15, 1999
A. Reutter, C. Barna , J. Schneider, T. Bohn
A Prototype of a Comprehensive Reuse System with Integrated Testbench Generation and Code Analysis
proceeding, Conference on System-Level Design, Antwerp, Belgium, September 22-24, 1999
G. Haug, U. Kebschull, W. Rosenstiel
VLIW Based Emulation of Digital Designs with the RAVE System
proceeding, International High Level Design Validation and Test Workshop, San Diego CA November 4-6 1999
R. Kress, G. Haug, U. Kebschull,W. Rosenstiel
Hardware/Software System Prototyping using VLIW Architectures
book, Business and Work in the Information Society / New technologies and Applications, J.-Y. Roger et. al. (Eds.), IOS Press, Amsterdam, ISBN 90 5199 491 5, 1999
C. Hansen , M. Uhlmann, W. Rosenstiel
An Interface Description Model for Reuse of Algorithmic Hardware Specifications
proceeding, Hardwarebeschreibungssprachen und Modellierungsparadigmen Workshop, Braunschweig, Deutschland, Februar 1999
C. Hansen , F. Nascimento, W. Rosenstiel
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications
proceeding, Proceedings of 36th Design Automation Conference (DAC), New Orleans (LA), USA
C. Hansen, W. Rosenstiel
A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis
proceeding, Forum on Design Languages (FDL'99), Lyon, Frankreich, September 1999
C. Buchholz, W. Rosenstiel
Application of Constraint Logic Programming in Allocation and Composition of Digital Designs
proceeding, IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France, 14-15 December, 1999
O. Bringmann , W. Rosenstiel
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
proceeding, Proceedings of 10th Workshop on Rapid System Prototyping, Clearwater, Florida, USA, 1999
O. Bringmann , W. Rosenstiel
Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen
proceeding, Informatik '99 - 29. Jahrestagung der Gesellschaft für Informatik, Informatik aktuell, Springer, 1999
C. Barna, W. Rosenstiel
Object-Oriented Reuse Methodology for VHDL
proceeding, Proceedings of Design, Automation and Test in Europe (D.A.T.E.), München, March 1999
C. Barna, W. Rosenstiel
Description and Classification of VHDL Objects in the Reuse Management System
proceeding, Hardwarebeschreibungssprachen und Modellierungsparadigmen Workshop, Braunschweig, Deutschland, Februar 1999
C. Barna, A. Reutter
Ein Effizientes Wiederverwendungssystem für den digitalen Schaltungsentwurf
proceeding, 2. Workshop zum Förderschwerpunkt "Smart Systems Engineering" (SSE), Berlin, Deutschland, April 1999
C. Barna
Reuse Automation
FZI internal, FZI Forschungsbericht Nr. 3-13-8/99
S. Schmitt, W. Rosenstiel
Der Einsatz von Jini für die Realisierung durchgängiger Steuerungskonzepte in verteilten eingebetteten Systemen
proceeding, JIT'99, Düsseldorf, September
S. Schmitt , W. Rosenstiel
Realisierungsmöglichkeiten eingebetteter Systeme im Internet
proceeding, GMM/GI/ITG Workshop Entwurf integrierter Schaltungen, Darmstadt, September 1999
A. Hergenhan, A. Siebenborn, W. Rosenstiel
Studies on Static Timing Analysis Techniques for Modern Processor Architectures
proceeding, WIP-Proceedings of the 20th IEEE Real-Time Systems Symposium, Phoenix, Arizona, USA, 1999
1998
K. Weiß, R. Kistner, W. Rosenstiel , A. Kunzmann
Analysis of the XC6000 Architecture for Embedded System Design
proceeding, IEEE Symposium on Field-Programmable Custom Computing Machines FCCM '98, Napa (CA), 1998
C. Trautwein , W. Rosenstiel
Elektronik-CAD-Anwendungen im WWW
proceeding, GI-Fachtagung, Tele- CAD - Produktentwicklung in Netzwerken (CAD '98), Darmstadt, M\344rz 1998
G. Koch, U. Kebschull , W. Rosenstiel
Breakpoints and Breakpoint Detection in Source Level Emulation
proceeding, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 3, No. 2, April 1998
A. Hergenhan, C. Weiler, K. Weiß, W. Rosenstiel
Value-Added Services for the Industrial Automation
proceeding, Proc. of Int. Workshop on Advanced Communication Services, Lisbon 1998
G. Haug, W. Rosenstiel
Reconfigurable Logic as Shared Resource for parallel Threads
proceeding, Proc. of the FCCM'98, Napa Valley April 1998
G. Haug, W. Rosenstiel
Reconfigurabale Hardware as Shared Resource in Multipurpose Computers
proceeding, in Field-Programmable Logic Applications Springer LNCS 1482 Heidelberg 1998
G. Haug , T. Buchholz, U. Kebschull , G. Koch , W. Rosenstiel
BehavioralEmulation of Synthesized RT--level Descriptions Using VLIW Architectures
proceeding, Proc of the 9th RSP, Leuven June 1998
C. Hansen, F. Nascimento, W. Rosenstiel
Verifying High-Level Synthesis Results Using a Partial Order Based Model
proceeding, High-Level Design Validation and Test Workshop '98, La Jolla (CA), USA
C. Hansen , A. Kunzmann, W. Rosenstiel
Verification by Simulation Comparison using Interface Synthesis
proceeding, Proceedings of Design, Automation and Test in Europe (D.A.T.E.), Paris 1998
C. Hansen , O. Bringmann
Spezifikation von VHDL-Verhaltensbeschreibungen für das High-Level Synthesesystem CADDY-II
FZI internal, FZI Forschungsbericht Nr. 5-13-10/98, Oktober 1998
O. Bringmann, W. Rosenstiel , D. Reichardt
Synchronization Detection for Multi-Process Hierarchical Synthesis
proceeding, Proceedings of International Symposium on System Synthesis (ISSS), Hsinchu, Taiwan 1998
O. Bringmann , W. Rosenstiel
Cross-Level Hierarchical High-Level Synthesis
proceeding, Proceedings of Design, Automation, and Test in Europe (D.A.T.E.), Paris 1998
1997
K. Weiß , A. Hergenhan , W. Rosenstiel
Systematischer Entwurf und Test eingebetteter Systeme am Beispiel eines ATM-Diagnosesystems
proceeding, Workshop Zielarchitekturen eingebetteter Systeme, Rostock Deutschland, September 1997
C. Weiler , A. Kunzmann, W. Rosenstiel
Performance Analysis for a Java-based Virtual Prototype
proceeding, International Workshop on Rapid System Prototyping, Cha pel Hill 1997
R. Seepold , A. Kunzmann, W. Rosenstiel
Eine effiziente objekt-orientierte Wiederverwendungsmethode für den Hardware-Entwurf
proceeding, 8. E.I.S.-Workshop, Universität Hamburg (Germany), 8. und 9. April 1997
W. Rosenstiel , C. Weiler
Java in Embedded Systems Design
proceeding, Proc. of SASIMI, Osaka, 1997
G. Koch , U. Kebschull, W. Rosenstiel
Co-Emulation and Debugging of HW/SW-Systems
proceeding, ISSS '97, Belgium-Antwerp, September 97
A. Kunzmann , W. Rosenstiel
Automatischer Taktzyklenabgleich zur Simulation in der High-Level Synthese
proceeding, Hardwarebeschreibungssprachen und Modellierungsparadigmen Workshop, Holzhau, Deutschland, Februar 1997
T. Buchholz, U. Kebschull , W. Rosenstiel
Emulation komplexer synthetisierter Schaltungen auf Signalprozessoren
proceeding, 8. E.I.S.-Workshop am 8. und 9. April 1997 an der Universität Hamburg
O. Bringmann , W. Rosenstiel
Resource Sharing in Hierarchical Synthesis
proceeding, Proceedings of International Conference on Computer Aided Design (ICCAD), San Jose 1997
1996
X. Xiong , P. Gutberlet , W. Rosenstiel
Automatic Generation of Interprocess Communication in the PARAGON system
proceeding, Proc. of the 7th IEEE int'l Workshop On Rapid System Prototyping, Thessaloniki, Greek, June, 1996
C. Trautwein , W. Rosenstiel
Regelung der Granularität paralleler verteilter Algorithmen
proceeding, MMB-Mitteilungen, Messung, Modellierung und Bewertung von Rechensystemen, No. 29, Frühjahr 1996
R. Seepold, A. Kunzmann, W. Rosenstiel
Hardware Design Methodology for Efficient Reuse
proceeding, 2nd World Conference on Integrated Design and Process Technology, p. 423-430, Austin (Texas, USA), Dec. 1996
A. Kunzmann , R. Seepold
An Alternative View on Weighted Random Pattern Testing
proceeding, IEEE Proceedings ASIC Conference, New York, September 1996
G. Koch , U. Weinmann, U. Kebschull, W. Rosenstiel
System prototyping in the COBRA project
article, Journal on Microprocessors and Microsystems, Elsevier, Vol. 20 No. 3, May 1996
G. Koch , U. Kebschull , W. Rosenstiel
Breakpoints and Breakpoint Detection in Source Level Emulation
proceeding, ISSS '96, USA-La Jolla (CA), November 96
A. Kunzmann, W. Rosenstiel
Reuse of Test Vectors for High Level Verification
proceeding, High Level Design Validation and Test Workshop '96, Oakland (CA), USA
J. Bullmann , U. Kebschull , W. Rosenstiel, Schubert
Library Based Technology Mapping Using Multiple Domain Representations
proceeding, EURO-DAC, CH-Geneva, 16.-29.09.1996
O. Bringmann, J. Engelhardt, R. Kumar, B. Mößner, W. Rosenstiel
Design of an Interrupt Controller with AC-8 Tools at Different Levels of Abstraction
proceeding, Workshop on Logic and Architecture Synthesis, Grenoble France, December 16-18 1996
1995
C. Weiler , U. Kebschull, W. Rosenstiel
C++ Base Classes for Specification, Simulation and Partitioning of a Hardware/Software System
proceeding, VLSI 95, Japan
U. Weinmann, O. Bringmann , W. Rosenstiel
Device Selection for System Partitioning
proceeding, Proceedings of EuroDAC, 1995
C. Trautwein , W. Rosenstiel
Auswahl des optimalen Algorithmus f\374r ein Netzwerk aus Workstations
proceeding, 40. IWK Ilmenau/Germany, Sep. 95
J. Schubert , A. Kunzmann , W. Rosenstiel
Reduced Design Time by Load Distribution with CAD Framework Methodology Information
proceeding, Eurodac '95, GB-Brighton, September 18-22, 1995
G. Koch , U. Kebschull, W. Rosenstiel
System Validation by Source Level Emulation of Behavioral VHDL Specifications
proceeding, 6th IEEE Intern. Workshop on Rapid System Prototyping, Chapel Hill, N. C., USA, 7-9 June 1995
G. Koch , U. Kebschull, W. Rosenstiel
Debugging Behavioral VHDL Specifications by Source Level Emulation
proceeding, Eurodac '95, GB-Brighton, September 18-22, 1995
C. Hansen , W. Rosenstiel, A. Ditzinger
Schaltungs-Synthese mit VHDL - Lösung der Entwurfsprobleme durch richtige Auswahl des Subsets
proceeding, CADS & SMT, 2/1995
C. Hansen , A. Ditzinger
Schaltungs-Synthese mit VHDL
proceeding, electronic industrie 6/1995
C. Hansen , O. Bringmann
Mit VHDL vom Algorithmus zur Schaltung
proceeding, Design & Elektronik - Zukunftstechnologien, 10/1995
C. Hansen
Mixed-Mode Design mit LOG/iC2
article, elektronic industrie 12/1995 Dezember 1995
F. Dresig, C. Hansen , U. Knüttel, A. Schmidt
Der FPGA-Report
article, Elektronik, 9/1995
E. Barros, W. Rosenstiel
A Clustering Approach to Support Hardware/Software Partitioning
article, Codesign - Computer - Aided Software/Hardware Engineering, ed. Jerzy Rosenblit and Klaus Buchenrieder, S. 230-262, IEEE Press, 1995
1994
M. Wendling, W. Rosenstiel, Mauer
A Hardware Environment for Prototyping and Partitioning Based on Multiple FPGAs
proceeding, EURO-DAC '94, Grenoble/Frankreich, September 1994
U. Weinmann, W. Rosenstiel
Network Flow base Clustering and Partitioning for FPGAs
proceeding, IFIP-Workshop on Logic and Archt. Synth., Grenoble, 1994
U. Weinmann, W. Rosenstiel
Logic Module Independent Mapping for Table-Lookup FPGAs
proceeding, ACM/SIGDA Workshop on FPGAs, Berkeley, 1994
U. Weinmann, W. Rosenstiel
Ein Partitionierungsystem für FPGA-Prototypenrealisierungen
proceeding, FPGA-Workshop, Karlsruhe, 1994
G. Koch , U. Kebschull , W. Rosenstiel
A Prototyping Environment for Hardware/Software Codesign in the COBRA Project
proceeding, CODES/CASHE, Grenoble, 1994
P. Gutberlet , W. Rosenstiel
Timing Preserving Interface Transformations for the Behavioural Synthesis of VHDL
proceeding, Proc. EURO-VHDL, 1994
P. Gutberlet , W. Rosenstiel
Specification of Interface Components for Synchronous Data Paths
proceeding, Proc. International Symposium on High-Level Synthesis, 1994
E. Barros, W. Rosenstiel, X. Xiong
A Method for Partitioning UNITY Language in Hardware and Software
proceeding, Proc. EURODAC, Grenoble, Sept. 1994
1993
U. Weinmann, W. Rosenstiel
Technology Mapping for Sequential Circuits Based on Retiming Techniques
proceeding, EURO-DAC 93, Hamburg, September 1993
C. Hansen , E. Barros.W. Rosenstiel
A Comparison of some specification Mechanisms to support Hardware/Software Codesign
proceeding, Second IFIP International Workshop on Hardware/Software Codesign Codes/CASHE 93, Innsbruck/\326sterreich 1993
P. Gutberlet , W. Rosenstiel
Interface Specification and Synthesis for VHDL Processes
proceeding, Proc. EURODAC, 1993
E. Barros, W. Rosenstiel
A Clustering Approach to Support Hardware/Software Partitioning
proceeding, Computer Aided Software/Hardware Engineering, IEEE Press, 1993
E. Barros, W. Rosenstiel, X. Xiong
Hardware/Software Partitioning with UNITY
proceeding, CODES'93, Cambridge, Massachusetts, Oct. 1993
1992
P. Gutberlet, W. Rosenstiel
Scheduling Between Basic Blocks in the CADDY Synthesis System
proceeding, Proc. EDAC, 1992
P. Gutberlet , J. Müller, H. Krämer, W. Rosenstiel
Automatic Module Allocation in High Level Synthesis
proceeding, Proc. EURODAC, 1992
E. Eschermann, O. Haberl, O. Bringmann , O. Seitz
COSIMA: A Self-Testable Simulated Annealing Processor for Universal Cost Functions
proceeding, Proceedings of EuroASIC, 1992
E. Barros, W. Rosenstiel
A Method for Hardware Software Partitioning
proceeding, CompEuro 92, 4.-8. Mai 92, S. 580-585, Den Haag 1992
1991
P. Gutberlet, H. Krämer, W. Rosenstiel
CASCH - a Scheduling Algorithm for High-Level Synthesis
proceeding, Proc. EDAC, 1991
1990
P. Gutberlet, H. Krämer, W. Rosenstiel
CASCH - ein Scheduling-Algorithmus für High-Level-Synthese
contribution to a book, in B. Reusch, "Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme", Springer, 1990