Modeling and Refinement of Embedded Platforms

As a consequence, future designs of microelectronic systems have to be done in the context of their embedding hardware and software system and have to consider the communication characteristics and requirements of their embedding environment. This step requires a paradigm shift of today's system design methods.

So, one part of the work addresses the specification and interconnection topology of distributed microelectronic systems. To cope with that modeling challenge a holistic modeling approach is used based on UML which combines both hardware and software view in an integrated system development process.

Due to the raising complexity of embedded systems, the use of virtual prototypes becomes more and more important to evaluation the entire system in an early design phase. In recent years, a design process has been introduced which considers the implementation of virtual prototypes at different levels of abstraction, the refinement between these abstraction levels and the generation of target software out of the VP models.

Current research objectives:

• Integration of different modeling languages ​​for integrated system design
• Corporate examination of software, operating system, network- and hardware platform

• Automatic Generation of Reference Models for Simulation and Verification

Verification Using Virtual Prototyping

Using virtual prototypes, the system functionality can be simulated together with the underlying hardware architecture at different levels of abstraction. The functional specification at system level can be mapped to an executable virtual prototype. The virtual prototype by itself can be refined to lower levels of abstraction. On the other hand, also an already configured system can (partially) be mapped onto a virtual prototype.

Current research objectives:

• Building virtual prototypes for fast and accurate system evaluation

• Integration of software or hardware models and konfigurable operating system models

• Support by different abstraction levels in one model

Architectural Analysis and Exploration

The steadily increasing chip complexity towards hundreds of millions transistors leads to a significant change in System-on-Chip (SoC) design. This development is enabled by advancements in technology. Caused by the steadily increasing number of transistors on a single chip, the designers of System-on-Chips are able to integrate more components like processor cores, DSP cores, memories, and specialized hardware on a single chip. The scalability of SoC declines with the number of components integrated onto a single chip connected to on-chip busses .

The platform as the result of the comprehensive modeling process can be optimized to meet overall system requirements. This means optimization of both the communication topology, mainly used in the mobile and multi-computing domain, and also the configuration of the communication architecture in the automotive domain. The optimization process is guided by a static communication and performance analysis based on an extended controlflow- and dataflow-graph representation of the system behavior including protocol mechanisms.

Current research objectives:

• Architectural exploration of System-on-Chip architectures and Network Topologies

• Determination of an optimised mapping of function blocks to the architectural components

• Automatic detection of bottlenecks, requirement violation and specification conflicts

Dependability-Driven Design

The utilization of cutting-edge manufacturing technologies for embedded systems becomes crucial when the manufacturing technology for nanoelectronic devices reaches physical limits. When advancing to a new technology node basically all design criteria improved during the last decades: smaller feature sizes meant higher integration, smaller delay, reduced power consumption, less per-transistor cost etc. From now on, however, shrinking feature sizes have strong effects on the reliability, like process variation, thermal issues, aging effects, soft errors caused by radiation, etc. We are currently at the verge of a major inflection point in designing embedded systems which consists of highly integrated circuits at its core and thus rely upon their unreliable behavior. Therefore, new design methods and tools are under intensive research to guarantee reliable and robust systems in spite of unsafe and faulty functions on the lowest process levels. Robustness verification becomes much more critical as soon as upcoming nanoelectronic devices will penetrate safety-critical embedded systems which actively interact with the human environment. Current research focuses on the application of accelerated stress tests directly acting onto the virtual prototype in order to derive early robustness predictions at electronic system level. Further activities are focusing on consideration of non-functional requirements like performance, power, temperature, and reliability into a seamless verification flow along the supply chain from the product integrator to the SoC supplier.

Current research objectives:

• Analysis of application specific parameters on dependability and robustness

• Methods for statical analysis and dynamic minimization of thermal stress factors

• Virtual qualification of a SoC using accelerated stress tests