Nadir Khan

Wissenschaftlicher Mitarbeiter

Werdegang

• Feb 2017 - to date: Research Scientist at FZI in the Embedded Systems and Sensor Engineering (ESS) department.
• 2016-2017: Senior Engineer, ARM Holdings plc - Trondheim, Norway
• 2013-2016: Design Engineer maXTouch, Atmel Corporation - Trondheim, Norway
• 2011-2013: Digital IC Design Engineer, TES Electronics Solutions GmbH - Berlin, Germany
• 2010: Master's degree in System on Chip Design, Lund University - Sweden
• 2008: Bachelor's degree in Computer Systems Engineering, UET Peshawar - Pakistan

Interests

• Hardware Architectures
• Signal/Image Processing
• Cryptography
• Reconfigurable Architectures
• Application Specific Reconfiguration

Publikationen

Zeitungs- oder Zeitschriftenartikel (2)

1. Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-per-Device IP Licensing SchemeInfoDetails

   Nadir Khan; Sven Nitzsche; Asier Garciandia López; Jürgen Becker, 2021

   A pay-per-use Intellectual Property (IP) licensing model that can protect IPs from multiple participants will benefit the FPGA IP market and Small to Medium Enterprises (SMEs). Existing protection solutions in modern FPGA devices rely on dedicated decryption engines that use cryptographic keys, which require programming them in a trusted environment. Since designs from multiple participants need protection in a typical licensing scenario, it requires a trusted third party for key programming and encryption tasks. These requirements led to the proposition of several licensing schemes; however, they do not address several security and flexibility challenges. Therefore, in this work, we propose a pay-per-device IP licensing scheme that is secure, less restrictive for the system developer and offers protection against malicious IP cores. The scheme relies on a Security Framework (SFW) that provides a Trusted Execution Environment (TEE), which handles key storage, cryptographic operations, and security monitoring. A device running the SFW can be considered a trusted platform that provides a direct secure path for the IP from its vendor to the device’s TEE, where it is decrypted, analyzed and, then configured on the programmable logic.

2. Automatic Floorplanning and Standalone Generation of Bitstream-Level IP CoresDetails

   Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, and Jürgen Becker, 2020

Konferenzbeitrag (7)

1. Moving Target and Implementation Diversity based Countermeasures against Side-Channel AttacksDetails

   Nadir Khan, Benjamin Hettwer and Juergen Becker, 2021

2. A Secure Framework with Remote Configuration of Intellectual PropertyInfoDetails

   Nadir Khan, Sven Nitzsche, Jürgen Becker, 2019

   In this work, an intellectual property (IP) licensing framework is proposed that is secure against IP theft (cloning and redistribution). This security is provided by utilizing built-in features of modern field programmable gate arrays (FPGAs), e.g. secure boot, state-of-the-art cryptography and trusted execution environments (TEE). The scheme is also the least restrictive in comparison to other publications in this area. Using this scheme, multiple IP core vendors (CVs) can configure their IPs remotely by connecting directly to an FPGA. Devices are booted securely using an authenticated and encrypted boot loader that initiates an authenticated and encrypted hypervisor, which in turn provides a TEE by partitioning the system resources into secure and non-secure sections. At this stage, a secure operating system (OS) is loaded that handles all the security critical functions such as communication with CVs, storage and analysis of bitstreams, enforcement of license constraints and configuration of IPs. Then, a second, non-secure OS is loaded, which provides an isolated execution environment with unrestricted access to non-secure resources. Hence, they are not limited to predefined APIs. Both OSes can interact via the hypervisor. The implementation of this framework is a work-in-progress and results presented within this paper are subject to change.

3. Secure Local Configuration of Intellectual Property Without a Trusted Third PartyDetails

   Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche and Jürgen Becker, 2019

4. Amplifying Side Channel Leakage by Hardware Modification of Xilinx Zynq-7 FPGA Evaluation BoardsDetails

   Nadir Khan, Sven Nitzsche, Raffaela Frank, Lars Bauer, Jörg Henkel, Jürgen Becker, 2019

5. Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCsDetails

   Arthur Silitonga, Zhou Jiang, Nadir Khan, Juergen Becker, 2019

6. Implementation of an SVD Based MIMO OFDM channel estimatorDetails

   Johan Löfgren, Shahid Mehmood, Nadir Khan, Babar Masood, M. Irfan Z. Awan, Imran Khan, Nafiz A. Chisty, Peter Nilsson, 2009

7. Effect of Increasing Number of Gaussian on Text-Independent GMM-Based Voice Recognition SystemDetails

   Sardar Ali, Mohammad Mustafa Bari, Nadir Mohammad Khan, Syed Waqar Shah, 2008

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Kontakt

Telefon: +49 721 9654-160
E-Mail: khan@dont-want-spam.fzi.de

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