Dr.-Ing. Carsten Tradowsky

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Carsten Tradowsky ist seit August 2016 als Ansprechpartner für den Forschungsbereich Embedded Systems and Sensors Engineering (ESS) beim Kompetenzzentrum IT-Sicherheit am FZI Forschungszentrum Informatik tätig.

Von Januar 2012 bis Juni 2016 war er als wissenschaftlicher Mitarbeiter am Institut für Technik der Informationsverarbeitung (ITIV) am Karlsruher Institut für Technologie (KIT) in der Forschungsgruppe von Prof. Becker tätig. Er arbeitete im DFG Sonderforschungsbereich/Transregio 89 'Invasive Computing' (InvasIC) im Teilprojekt 'Adaptive Application-Specific Invasive Microarchitecture', dem DAAD Programm Hochschulpartnerschaften mit Griechenland TEAChER 'TEach AdvanCEd Reconfigurable architectures and tools' und an Industriekooperationen mit. Er betreute die Lehrveranstaltungen 'Hardware/Software Co-Design', die ITIV Student Labs rund um die 'TivSeg' Plattform und das Projektpraktikum 'Praktikum Informationstechnik'. Im Jahr 2016 erhält er das 'BaWue-Zertifikat für Hochschuldidaktik'. Er ist Koauthor von Veröffentlichungen und Patenten. 2013 hat er am Karlsruhe House of Young Scientists (KHYS) Programm 'Kontakte knüpfen' teilgenommen.

Zuvor studierte er am KIT Elektro- und Informationstechnik mit der Vertiefungsrichtung System-on-Chip. Das schloss er im August 2011 mit der Diplomarbeit 'Entwurf und Modellierung einer laufzeitadaptiven Prozessorpipeline auf Basis des LEON3' ab. Zusätzlich belegte er am Zentrum für Angewandte Kulturwissenschaft und Studium Generale (ZAK) das Modul 'Führungskompetenz und unternehmerisches Denken' (FunD).

Publications

Books (5)

1. A Novel ADL-based Approach to Design Adaptive Application-Specific Processors (forthcoming)Details

   C. Tradowsky and T. Harbaum and L. Masing and J. Becker, Springer International Publishing, 2016

2. A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core SystemsDetails

   Tradowsky, Carsten and Cordero, Enrique and Orsinger, Christoph and Vesper, Malte and Becker, Jürgen, Springer International Publishing, 2016

3. Adaptive Cache StructuresDetails

   Tradowsky, Carsten and Cordero, Enrique and Orsinger, Christoph and Vesper, Malte and Becker, Jürgen, Springer International Publishing, 2016

4. A Novel Concept for Adaptive Signal Processing on Reconfigurable HardwareDetails

   Figuli, Peter and Tradowsky, Carsten and Martinez, Jose and Sidiropoulos, Harry and Siozios, Kostas and Stenschke, Holger and Soudris, Dimitrios and Becker, Jürgen, Springer International Publishing, 2015

5. TEAChER: TEach AdvanCEd Reconfigurable Architectures and ToolsDetails

   Siozios, Kostas and Figuli, Peter and Sidiropoulos, Harry and Tradowsky, Carsten and Diamantopoulos, Dionysios and Maragos, Konstantinos and Delicia, Shalina Percy and Soudris, Dimitrios and Becker, Jürgen, Springer International Publishing, 2015

Articles (3)

1. The Road to "ITIV Labs" -- an Integrated Concept for Project-Oriented Systems Engineering Education (Best Paper of the Session Award from the Committee of ICMEI 2014)Details

   T. Beuth and T. Gaedeke and C. Tradowsky and J. E. Becker and A. Klimm and O. Sander, 2015

2. Porter for the ITIV LABS -- Objective-Related Engineering Education in an Undergraduate LaboratoryDetails

   Tradowsky, Carsten and Lauber, Andreas and Werner, Stephan and Beuth, Thorsten and Müller-Glaser, Klaus D. and Sax, Eric, 2015

3. Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level MicroarchitecturesDetails

   G. Shalina Percy Delicia and Thomas Bruckschloegl and Peter Figuli and Carsten Tradowsky and Gabriel Marchesan Almeida and Juergen Becker, 2013

Conference Proceedings (7)

1. Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-coresInfoDetails

   M. Mohr and C. Tradowsky, 2017

   To improve scalability, some many-core architectures abandon global cache coherence, but still provide a shared address space. Partitioning the shared memory and communicating via messages is a safe way of programming such machines. However, accessing pointered data structures from a foreign memory partition is expensive due to the required serialization. In this paper, we propose a novel data transfer technique that avoids serialization overhead for pointered data structures by managing cache coherence in software at object granularity. We show that for PGAS programming languages, the compiler and runtime system can completely handle the necessary cache management, thus requiring no changes to application code. Moreover, we explain how cache operations working on address ranges complement our data transfer technique. We propose a novel non-blocking implementation of range-based cache operations by offloading them to an enhanced cache controller. We evaluate our approach on a non-cache-coherent many-core architecture using a distributed-kernel benchmark suite and demonstrate a reduction of communication time of up to 39.8%.

2. SmartLoCore: A Concept for an Adaptive Power-Aware Localization ProcessorDetails

   C. Tradowsky and T. Gädeke and T. Bruckschlögl and W. Stork and K. D. Müller-Glaser and J. Becker, 2014

3. ViSA: A highly efficient slot architecture enabling multi-objective ASIP coresDetails

   P. Figuli and C. Tradowsky and N. Gaertner and J. Becker, 2013

4. Adaptive processor architecture - invited paperDetails

   M. Hübner and D. Goehringer and C. Tradowsky and J. Henkel and J. Becker, 2012

5. On Dynamic Run-time Processor Pipeline ReconfigurationDetails

   C. Tradowsky and F. Thoma and M. Hübner and J. Becker, 2012

6. LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture (Best Work-in-Progress (WiP) Paper Award)Details

   Carsten Tradowsky and Florian Thoma and Michael Hübner and Jürgen Becker, 2012

7. Dynamic Processor ReconfigurationDetails

   M. Hübner and C. Tradowsky and D. Gohringer and L. Braun and F. Thoma and J. Henkel and J. Becker, 2011

Theses (1)

1. Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver ProzessorplattformenDetails

   Tradowsky, Carsten, 2016

Others (2)

1. Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cellsDetails

   Biggs, John Philip and Myers, James Edward and Howard, David William and Flynn, David Walter and Tradowsky, Carsten, 2013

2. Apparatus for storing a data value in a retention modeDetails

   James Edward Myers and Biggs, John Philip and Flynn, David Walter and Tradowsky, Carsten, 2013

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Kontakt

E-Mail: Carsten.Tradowsky@dont-want-spam.fzi.de

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