Dipl.-Inform. Sebastian Ottlik

Wissenschaftlicher Mitarbeiter

Werdegang

Von April 2011 bis Dezember 2012 arbeitete Sebastian Ottlik als wissenschaftliche Hilfskraft in der Abteilung Systementwurf in der Mikroelektronik (SIM) des FZI. Dort verfasste er auch seine Diplomarbeit mit dem Titel  "Erweiterung eines Instruktionssatzsimulators zur Bestimmung der Ausführungszeit von Programmen". Nach Abschluss seines Studiums der Informatik mit den Vertiefungsfächern Betriebssysteme und Übersetzerbau, begann er im Januar 2013 seine Tätigkeit als wissenschaftlicher Mittarbeiter in der Abteilung SIM des FZI.

Forschungsinteressen

• Simulation von Programmausführungen
• Virtuelle Prototypen
• Programmanalyse
• Eingebettete Systeme
• Übersetzerbau

Publikationen

Buch (3)

1. Timing Models for Fast Embedded Software Performance AnalysisDetails

   Oliver Bringmann and Christoph Gerum and Sebastian Ottlik, Springer, 2017

2. Precise Software Timing Simulation Considering Execution ContextsDetails

   Oliver Bringmann and Sebastian Ottlik and Alexander Viehl, Springer, 2017

3. Advanced System-Level Design for Automated DrivingDetails

   Jan Micha Borrmann and Sebastian Ottlik and Alexander Viehl and Oliver Bringmann and Wolfgang Rosenstiel, Springer, 2017

Konferenzbeitrag (4)

1. Context-Sensitive Timing Automata for Fast Source Level SimulationInfoDetails

   Sebastian Ottlik and Christoph Gerum and Alexander Viehl and Wolfgang Rosenstiel and Oliver Bringmann, 2017

   We present a novel technique for efficient source level timing simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level timing simulation. However, a direct application of the binary level approach to source level simulation reduces simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based simulation technique. The proposed contextsensitive timing automata enable an efficient evaluation of complex simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache simulation. The accelerated simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.

2. Trace-based context-sensitive timing simulation considering execution path variationsInfoDetails

   Sebastian Ottlik and Jan Micha Borrmann and Sadik Asbach and Alexander Viehl and Wolfgang Rosenstiel and Oliver Bringmann, 2016

   We present a fast and accurate timing simulation of binary code execution on complex embedded processors. Underlying block timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on timings observed in one hardware execution, timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.

3. Context-sensitive Timing Simulation of Binary Embedded SoftwareInfoDetails

   Sebastian Ottlik and Stefan Stattelmann and Alexander Viehl and Wolfgang Rosenstiel and Oliver Bringmann, ACM, 2014

   We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

4. Combining instruction set simulation and WCET analysis for embedded software performance estimationInfoDetails

   Stefan Stattelmann and Sebastian Ottlik and Alexander Viehl and Oliver Bringmann and Wolfgang Rosenstiel, 2012

   The software complexity of MPSoCs is increasing dramatically, resulting in new design challenges, such as improving the system's performance and programmability by porting parallel programming APIs. Such challenges impose more time and cost on the system's software development. This leads to the adopting of virtual platform frameworks aimed at functional verification like OVP, capable of simulating embedded systems running real application code at the speed of hundreds of MIPS. This work focuses on enhancing OVP capability by including a quasi-cycle accurate timing CPU model, making it suitable for performance analysis. This paper also evaluates the accuracy of the proposed timing CPU model when compared to a real system. Results show that the accuracy of our model varies from 0.06% to 10.56% depending on the benchmark profile.

Thesis (1)

1. Erweiterung eines Instruktionssatzsimulators zur Bestimmung der Ausführungszeit von ProgrammenDetails

   Sebastian Ottlik, 2012

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Kontakt

Telefon: +49 721 9654-426
E-Mail: ottlik@dont-want-spam.fzi.de

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